A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. The drive toward this ultra large scale integration has resulted in continued down-scaling or shrinking of device and circuit dimensions and features. One potential limiting factor associated with the down-scaling is the use of multiple-layers of interconnect required to complete the integrated circuit by connecting the various semiconductor devices together.
As is known in the art, if the average interconnect length can be reduced along with the dimensions of the devices then performance is typically enhanced. This has resulted in the use of multiple-layers of interconnects. These multiple-layers of interconnects can be very complex for certain types of integrated circuits. Moreover, as the device dimensions are scaled down, the structure of the interconnects becomes more complicated. By way of example, the dimensions of the interconnects needs to match the reduced dimensions of the devices. Additionally, as the number of devices to be connected is increased, so too is the number of interconnects increased. Since the typical circuit die size is not proportionally increased as the number of devices are increased, the current trend is to increase the number of interconnecting layers so as to provide the additional interconnects required. Thus, there is a need for improved methods and arrangements for fabricating multiple-levels of interconnects so as to further scale-down the integrated circuit size and increase performance, without compromising the yield of the manufacturing process and the reliability of integrated circuits.